After building a couple of more traditional clocks over the years ... The counter chain that accumulates the time is implemented in an FPGA — admittedly overkill, but [zaphod] wanted to learn ...

He wondered if he could do the same on an FPGA, and how hard it would be to count high clock rates. As it turns out, it’s pretty hard with a naive solution. Being a bit more clever turns the ...

The high bit rates can be achieved with a relatively slow FPGA clock frequency, trading off FPGA resources for simple timing closure. Data rate at the MIPI DPHY lanes, in bps, equals to L*bps, where L ...

Also, if at all there are inter FPGA clocks i.e. there is a clock that originates in one FPGA and needs to be used by the logic in the other FPGA there can be issues regarding timings and data ...